In the semiconductor packaging field, improvement in electrical transmission is always considered as an important factor for advancing the performance of electronic products. For example of the QFN (Quad Flat Non-leaded) technology disclosed in U.S. Pat. Nos. 5,942,794, 6,081,029 and 6,281,047, which improves a conventional lead-frame-based package such as QFP (Quad Flat Package) to allow a bottom surface of the lead frame to be directly exposed and reduce the length of leads of the lead frame, such that signal paths can be shortened and noises are diminished as well as a chip incorporated in the package can be made similar in size to a carrier, thereby facilitating the development of Chip Scale Package (CSP).
FIG. 4 illustrates a cross-sectional view of a QFN package, comprising a die pad 50 and a chip 51 attached to the die pad 50, wherein a plurality of leads 52 are disposed around the die pad 50, and the chip 51 is electrically connected to the leads 52 respectively by bonding wires 53; and an encapsulant 54 for encapsulating the chip 51, with bottom surfaces of the leads 52 and die pad 50 being exposed from the encapsulant 54. The use of such leads 52 eliminates a drawback in electrical performance caused by a conventional lead frame having a plurality of outer leads, simplifies the fabrication processes, and allows this package with advantages in electrical transmission to be applied to a high frequency product such as one employing radio frequency (RF).
However, along with the evolution of high frequency electronic products, the QFN package has encountered bottleneck in terms of electrical performance. This is because for upgrading the performance of the package, the number of I/O (input/output) connections is increased, which requires the leads to be arranged in multiple rows as disclosed in U.S. Pat. Nos. 6,225,146, 6,229,200 and 6,348,726. FIG. 5 shows a cross-sectional view of a package with a three-row arrangement of leads, wherein different sets of bonding wires 53, 53′, 53″ having different lengths are respectively electrically connected from a chip 51 to different rows of leads 52, 52′, 52″. This design obviously makes the wires 53″ connected to the outmost row of leads 52″ be excessively long, leading to an increase in insertion loss and electromagnetic interference. Moreover, since adjacent wires connected to different rows of leads have different lengths (i.e. the wires 53, 53′, 53″ are different in length), signal transmission paths are different in distance and time for transmitting RF differential pair signals is varied. This greatly affects the electrical performance of high frequency products, and makes the QFN package not suitable for new generation of high frequency electronic products.
In addition, U.S. Pat. No. 6,191,477 has proposed a land grid array (LGA) semiconductor package using a substrate as a carrier, which can be applied to high frequency products as similarly having shortened signal paths. FIG. 6 illustrates a cross-sectional view of such package, wherein the substrate 60 is formed with a plurality of pads 61 located beside conductive vias 62 on an upper surface of the substrate 60, and a plurality of lands 63 located beside the corresponding conductive vias 62 on a lower surface of the substrate 60, such that the number of conductive traces is reduced, and signals can be transmitted directly through the pads 61, the conductive vias 62, and the lands 63 to the outside without requiring the conductive traces.
However, similarly to the QFN packages, for upgrading the performance of the LGA package, the number of I/O connections is increased, which requires the pads 61 and the lands 63 to be disposed in multiple rows, for example, a double-row arrangement of the lands shown in FIG. 7. This results in the same problem of electrical performance for the LGA package. Since a chip 64 is electrically connected to the pads 61, 61′ of the two rows respectively by different sets of bonding wires 65, 65′ having different lengths as shown in FIGS. 8A and 8B, and is further electrically connected to the lands 63 on the lower surface of the substrate 60 by the conductive vias 62. The wires 65′ connected to the outer row of lands 61′ are relatively longer and may cause insertion loss and electromagnetic interference. Moreover, due to the different lengths of the adjacent wires 65, 65′ connected to different rows of the lands 61, 61′, time for transmitting RF differential pair signals is varied, and the signal quality would be degraded, making the LGA package not suitable for new generation of high frequency electronic products.
Therefore, the problem to be solved herein is to provide a novel high electrical performance semiconductor package suitable for high frequency products, which has improved electrical performance and avoids lengthy wires and varied signal transmission time.